Conventionally, a memory operation is guaranteed by performing a memory operation test to detect error bits, and rejecting the error bits. Such a memory operation test is performed before shipping the memory per unit of memory.
Specifically, a memory control apparatus connected to the memory generates a predetermined test pattern, operates the memory on the basis of the generated test pattern, and performs a plurality of test items. When the memory has passed the test items, the memory which has passed the test items is shipped and installed in an information processing system.
An example of a conventional memory test will be described specifically with reference to FIG. 15. FIG. 15 is a diagram for explaining a conventional technique. As illustrated in FIG. 15, the memory control apparatus generates a predetermined test pattern and transmits a data write address (shown as “ADD” in FIG. 15), a command for write instruction (shown as “COM” in FIG. 15), and write data to the memory device to be tested. Thereafter, the memory device transmits read data to the memory control apparatus.
When receiving the read data, the memory control apparatus checks whether the read data is correct, and determines whether the test is passed. As a result, when the tested memory is determined to pass the test, the tested memory is shipped.
Japanese Laid-open Patent Publication No. 2008-269669 and Japanese Laid-open Patent Publication No. 2008-84425 are examples of related art.
In the above described conventional technique, a memory operation test is performed per unit of memory by using a predetermined test pattern. Therefore, although the memory has no error in the test result of the test, an error may occur after the shipment of the memory. In other words, there is a difference between an operating environment in which the test is performed and an operating environment in which the memory is actually used, and hence an error may occur after shipment of the product even though there is no error in the test result. Therefore, there is a problem that the memory operation may not be appropriately guaranteed.